1. Field of the Invention
The present invention relates to power semiconductor devices and methods of manufacturing the same, in particular, to a power semiconductor device having a metal-oxide semiconductor gate or “MOS-gate” structure, and a manufacturing method therefor.
2. Description of the Related Art
In recent years, as power semiconductor devices used for electric-power conversion and controls by inverters or the like, insulated gate bipolar transistors (IGBTs) are utilized that enable fast (high-speed) operations and high withstand (blocking) voltage. And then, among these IGBTs, recently, in place of an IGBT of a planar type (planar IGBT), an IGBT of a trench-gate type that has high electron-supplying capacity is widely utilized.
A typical structure for an IGBT of a trench-gate type, such as the trench-gate IGBT (TIGBT) described above, is shown, for example, in Non-Patent Publication “Transistor Technology SPECIAL,” No. 85, Jan. 1, 2004, p. 45 (FIGS. 3-11), CQ Publishing Co., Ltd., Tokyo, Japan.
A vertically cross-sectional view outlining a structure of the trench-gate IGBT is shown in FIG. 73. As shown in FIG. 73, in the trench-gate IGBT, an n+ buffer layer 102 is provided upon a first main surface (namely, the top-side surface in the figure) of a p+ substrate 101; an n− layer 103 is provided upon the n+ buffer layer 102; a p base layer 104 is provided upon the n− layer 103; and n+ emitter regions 105 are provided in the top side of the p base layer 104.
And then, trench gates 106 are provided; each having a trench 106a that adjoins to the n+ emitter regions 105, passes through the p base layer 104 and reaches into the n− layer 103; a gate insulation film 106b is provided to cover the inner surface of the trench 106a; and an gate electrode 106c is provided with which the space inside surrounded by the gate insulation film 106b is filled.
Moreover, interlayer insulation films 107 are provided to cover a large part of each top-side of the n+ emitter regions 105, and each top side of the trench gates 106; in addition, an emitter electrode 108 is provided to cover the remaining part of the top-side surface of the +n+ emitter regions 105 (not covered by the interlayer insulation films 107), the entire surface of the interlayer insulation films 107, and the remaining top side of the p base layer 104. Furthermore, a collector electrode 109 is provided on a second main surface (namely, the bottom-side surface in the figure) of the p+ substrate 101.